2D FIR filter test bench address out of bound

[Altera_Forum]

Working with the 2D fir filter test-bench (from video and image processing suite). Configured the lpm resolution to be 640.  

Issue is that data_out goes high impedance at regular intervals and the dout_valid does not transition low.  

• valid data output for 638 clock cycles 
• then output is undefined for 386 clock cycles 
• these two intervals sum to 1024 (maybe there's a 10 bit address counter even though I've asked for 640 sized image?) 
• after 16 "lines": din_ready transitions low, then din_valid goes low, and finally dout_valid drops low 

 Modelsim complains about out of bounds addressing errors:  "Address pointed at port A is out of bound!"  "Address pointed at port B is out of bound!"  I don't understand why the output data is undefined while the dout_valid signal is still logic 1. A modelsim screen-shot is attached.   

[Altera_Forum]

without the code - we cannot tell. Post the code so we can have a look.

[Altera_Forum]

your question should not be why data... but your address is wrong when pointed at i.e. your counter points to address value > memory size.

[Altera_Forum]

Working with the 2D fir filter test-bench (from video and image processing suite). Configured the lpm resolution to be 640.  

Issue is that data_out goes high impedance at regular intervals and the dout_valid does not transition low.  

• valid data output for 638 clock cycles 
• then output is undefined for 386 clock cycles 
• these two intervals sum to 1024 (maybe there's a 10 bit address counter even though I've asked for 640 sized image?) 
• after 16 "lines": din_ready transitions low, then din_valid goes low, and finally dout_valid drops low 

 Modelsim complains about out of bounds addressing errors:  "Address pointed at port A is out of bound!"  "Address pointed at port B is out of bound!"  I don't understand why the output data is undefined while the dout_valid signal is still logic 1. A modelsim screen-shot is attached.   ---- Note that I do not control the addressing -- rather the Altera generated lpm block controls the addressing. I am simply controlling with the Avalon packet transfer interface. So my question is why is the auto-generated MegaWizard making a mistake with the addressing?  I've attached the auto-generated verilog files. The auto-generated *.vo file is nearly impossible to read.