I generated all of the necessary files to simulate the SerialLite II IP from MegaWizard. Everything went smoothly, but when I run the TCL script to simulate in Questa, I get the following errors:# ** Error: SerialLiteII_tb.v(514): (vopt-2135) Too many port connections. Expected 51, found 56.# # ** Error: SerialLiteII_tb.v(594): (vopt-2135) Too many port connections. Expected 53, found 58. They're in reference to the contents of the generated files SerialLiteII.vo and SerialLiteII_sister_slite2_top.vo. I went through the contents of both vo files and the testbench and noticed that there are some major differences between the module declarations in the .vo files and the instantiation of them in the testbench. Has anyone ever run into this problem before? For reference, here are the parameters defined in MW: -Quartus II V13.1 -Device: Stratix V -Data rate: 6375 Mbps -Transfer size: 1 column -Bidirectional port type -12 lanes each, tx and rx -Data packets only Thanks in advance.
- Stratix® V FPGAs
I can't be the only one who has ever tried to simulate SerialLite II before... no one has any insight? How is it possible that the files that the MegaWizard are generating are so incorrectly implemented that a proper simulation can't even begin? I have to be doing something incorrectly here, but there are so few options to choose while setting it up that I'm not sure what could be wrong.