3 PLL cascading.

[AGofs]

Is it possible to cascade 3 PLL's?

If yes, how should I define the middle PLL?

What BW (High,Low,Auto etc) should I define for it?

Are there some additional definitions?

[Rahul_S_Intel1]

Hi ,

Kindly find the cascading support for PLL in the below document in that Upstream PLL and Down stream PLL is provided that means to say only two PLL .

Page no: 11

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf

[Rahul_S_Intel1]

Hi ,

 Kindly let me know, if you need further assistance.