FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

3 PLL cascading.

AGofs
Novice
250 Views

Is it possible to cascade 3 PLL's?

If yes, how should I define the middle PLL?

What BW (High,Low,Auto etc) should I define for it?

Are there some additional definitions?

0 Kudos
2 Replies
Rahul_S_Intel1
Employee
110 Views

Hi ,

Kindly find the cascading support for PLL in the below document in that Upstream PLL and Down stream PLL is provided that means to say only two PLL .

Page no: 11

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf

 

Rahul_S_Intel1
Employee
110 Views

Hi ,

 

 Kindly let me know, if you need further assistance.

Reply