- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Is it possible to cascade 3 PLL's?
If yes, how should I define the middle PLL?
What BW (High,Low,Auto etc) should I define for it?
Are there some additional definitions?
Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ,
Kindly find the cascading support for PLL in the below document in that Upstream PLL and Down stream PLL is provided that means to say only two PLL .
Page no: 11
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ,
Kindly let me know, if you need further assistance.
![](/skins/images/D3C0B914909A6564BBB97F4AD1ED1973/responsive_peak/images/icon_anonymous_message.png)
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page