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I'm currently using the ALTFP_CONVERT megafunction in my design to convert a 10 bit integer to a 32bit FP. It has a clk_en (convert_en) and an aclr port (convert_rst).
Unfortunatly the output stays at high impedance (as shown in the attachment). I get the following warning during the simulation setup: --- Quote Start --- # ** Warning: (vsim-8607) c:/altera/11.1/modelsim_ase/win32aloem/../altera/verilog/src/cycloneiii_atoms.v(6155): Non-positive replication multiplier inside concat. Replication will be ignored. --- Quote End --- which I don't really understand at all. Could that be related? Or is there something else I'm missing? Thanks in advance :)Link Copied
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You are not showing the output port of the altfp_convert megafunction. I don't think, that the output of altfp_convert is tri-stateable, apparently it's sourced from a register.
It's also not clear, if the warning is generated during processing of the MegaFunction or other parts of your design.- Mark as New
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Thank you for your reply.
The section of my testbench for stimulating the convertor: --- Quote Start --- //Convert signals logic convert_rst; logic convert_en; logic[9:0] in; logic [31:0] out; //Module fpconvert converter(convert_rst,CLOCK_50,convert_en,in,out); //Convert Signals initial begin convert_rst = 1'b0; convert_en = 1'b0; in = 10'b0000000001; # 50ns; convert_rst = 1'b0; convert_en = 1'b1; in = 10'b0000100001; # 50ns; convert_rst = 1'b0; convert_en = 1'b1; in = 10'b0000100001; # 50ns; convert_rst = 1'b0; convert_en = 1'b1; in = 10'b0000100001; # 50ns; convert_rst = 1'b0; convert_en = 1'b1; in = 10'b0000100001; # 50ns; convert_rst = 1'b0; convert_en = 1'b1; in = 10'b0000100001; # 50ns; convert_rst = 1'b0; convert_en = 1'b1; in = 10'b0000100001; # 50ns; convert_rst = 1'b0; convert_en = 1'b1; in = 10'b0000100001; end --- Quote End --- As you can see, it is the megafunction output port which is high Z. I tried simulating without the 'mains' module (which is my entire design) which removed the 'Non-positive replication multiplier inside concat' error. So from what I can tell, it's a either an issue with the Megafunction or Modelsim.- Mark as New
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Problem solved. I made a new copy of ALTFP_CONVERT with a different name and that seemed to fix it. Surprising how changing the name of a module seems to fix things... I have a feeling I may have made an incorrect port assignment in another module, which messed up the synthesis of ALTFP_CONVERT when I tried testing it by itself in modelsim.
Thank you for your help :)
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