ASI output IP - Easy to use?

[Altera_Forum]

Hi, I am new to Altera solutions, but I was looking for an "easy way" to convert parallel TTL (even LVDS) to ASI Out. I found the ASI IP but I am not sure how easy it is to integrate, I mean, if it is "ready-to-use". Could anyone help me on this? 

 Regards,  Thiago

[Altera_Forum]

By ASI-out, you mean this video interface? 

 http://www.tvtechnology.com/article/12126  What IP are you referring to?  I see you have not posted enough yet to be able to include links, but you could provide a little more information on the source of the IP.  Do you have a board that has an ASI-Out interface? The article comments that it use 75-ohm transmission lines and is similar to SDI. The Stratix IV GX board has an SDI interface that uses external drivers interfaced to transceiver channels. Do you have something similar?  Cheers. Dave

[Altera_Forum]

Hello, 

 Sorry for the lack of info. Actually, what I need is to convert the parallel transport stream coming out of a digital tv demodulator into ASI. It should be very simple, 1 parallel In 1 ASI Out, maybe it is possible to use a very cheap FPGA. The ASI IP that I´ve seen only works with video conversion, or IP (Internet Protocol) bridge. I was trying to accomplish that using HOTLink from Cypress, but the FPGA is the correct way to make it work.  Regards,  Thiago

[Altera_Forum]

--- Quote Start ---   Actually, what I need is to convert the parallel transport stream coming out of a digital tv demodulator into ASI. It should be very simple, 1 parallel In 1 ASI    --- Quote End ---    That is still not much information.  I'm looking for things like;   * I need to take a 3.3V single-ended 16-bit parallel data stream at XXX MHz  * 8/10B encoded into YYY format packets, and   * transmit at a serial data rate of ZZZ using 75-ohm transmission line drivers  Then you can get feedback on which FPGA is appropriate.  Cheers, Dave

[Altera_Forum]

ASI core is very easy to use. Just give it 8bit parallel video data and generate required clocks. Thats it, works in 5 minutes.

[Altera_Forum]

Hi Dave, the SPI output from the demodulator has the attached waveform. 

It is simple: 8 bits data, CLK, sync byte, valid byte. The CLK frequency is around 5 MHz. TTL levels. And the DVB-ASI output is based on a standard I guess, not much to work on here.  Socrates, which ASI IP are you reffering to? The one available at Altera? It would be better if it was free :-P  Is it easy to configure the Transport Stream input?  Regards,  Thiago

[Altera_Forum]

Hi Thiago, 

   --- Quote Start ---   The SPI output from the demodulator has the attached waveform. It is simple: 8 bits data, CLK, sync byte, valid byte. The CLK frequency is around 5 MHz. TTL levels.   --- Quote End ---  That can easily be captured using a low-end FPGA or CPLD.    --- Quote Start ---   It would be better if it was free :-P   --- Quote End ---  If you know what you have to do to reformat the data, then it would be easy to write your own. You could always create a simulation with the Altera ASI IP code, and look at what the output data stream looks like for your given input data, and then write a core to reproduce that functionality.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Hi Thiago,  If you know what you have to do to reformat the data, then it would be easy to write your own. You could always create a simulation with the Altera ASI IP code, and look at what the output data stream looks like for your given input data, and then write a core to reproduce that functionality.  Cheers, Dave  --- Quote End ---    So there is none ready to use? I still have to code some parts of it?  Regards,

[Altera_Forum]

--- Quote Start ---  So there is none ready to use? I still have to code some parts of it?   --- Quote End ---    There is an Altera IP core;  http://www.altera.com/products/ip/iup/additional_functions_iup/m-alt-asi.html  Go and use it. That page indicates there is an open-core evaluation version, which means it is not free.   If you want free, then you have to decide what to do next.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  So there is none ready to use? I still have to code some parts of it?  Regards,  --- Quote End ---    The Altera ASI core is ready to use.  What do You mean by configuring transport stream? What do You need to configure there? ASI core takes clock and data (start is not required). Just connect the signals and it does its job.

[Altera_Forum]

Thiago, 

 Could you run the Open IP Core ? When i try to compile the ASI MegaCore i got the following error: Error (20005): A license file is required to enable compilation of your design for the Cyclone family of devices  It was waited :-)  I could not identify in altera documentation how to run the open core ASI. Somebody had success in this mission ? Somebody can indicate a documentation that could help me to compile and simulate Open Core ASI in Quartus II 11.0 web edition.  Thanks,  Best regards

[Altera_Forum]

I'm also trying to make a SPI-ASI converter in FPGA in my mastering work. 

So i'd like to use the open-core ASI evolution receiver on my system.   The altera documention gives an overview at OpenCore Plus Evaluation of Megafunctions documentation.   But i could not identify in Quartus II what are the steps necessary to compile and simulate the core.  Any help is welcome.  Thanks a lot,  Best Regards.

[Altera_Forum]

Use MegaWizard and generate ASI core.