FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6356 Discussions

ALTLVDS_RX doesn't compile

Altera_Forum
Honored Contributor II
841 Views

Hi, 

 

I'm trying to implement the ALTLVDS_RX IP using an external PLL and I get the following error if I enable the option "Use 'rx_data_reset' input port": 

 

Error (287102): Input pin "rx_data_reset" cannot be assigned a value 

Error (287103): Input port "auto_generated.rx_data_reset" cannot be used as a value 

Error (287103): Input port "auto_generated.rx_data_reset" cannot be used as a value 

 

The following assignment in line 741 of the file altlvds_rx.tdf seem to be wrong: 

IF USED(rx_data_reset) GENERATE 

rx_data_reset = auto_generated.rx_data_reset; 

END GENERATE; 

 

Quartus Version: 11.1 Service Pack 2.11 

FPGA: Cyclone IV GX 

 

Ralf
0 Kudos
0 Replies
Reply