FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

ALTMEMPHY DDR2 Performance on Cyclone-III

Altera_Forum
Honored Contributor II
918 Views

Hi 

 

I have a design, using DDR2 and ALTMEMPHY on the Cyclone-III. My DDR2 IOs are on the side of FPGA (Row IO). According to the 2008 release of AN-445, maximum clock rate of the ALTMEMPHY is 167 MHz for side IOs, 150 for Wraparound IOs, and 200 for top/bottom IOs. 

AN-445 of 2009 has increased max. clock rate to 167 for wraparound IOs. There is no newer release of this AN. 

On the other hand, on the Cyclone-III latest handbooks or datasheets there is no information on the maximum clock rate of ALTMEMPHY. 

 

I need 200 MHz clock rate for my DDR2 interface which is on the row IO, but I cannot be sure its timing is met on the memory side (due to the ambiguity of the datasheet). 

 

What is the maximum clock rate of DDR2 ALTMEMPHY on Cyclone-III devices? 

 

Thanks
0 Kudos
0 Replies
Reply