AN744 Arria10 - IEEE1588 Design

[Ftiglius]

Hi to everyone! I ported AN744 design on my Arria10 PCB, with 2 GX channels. It runs fine: closing SFP+ plugs with cross fibre cables, I perform 1588 test, by TCL command.

it finish test succesfully , with 40/39 nsecs of time delay reported. I see that this design performs OneStep IEEE1588 sync, using PTP frames IEEE802.3 with no payload. I wish to add some user payload to this design, but it is really difficult, because it uses generator/monitor on parallel 64 bit (so, speed is 64x126 Mhz = 8 Gbps). Data are converted 64/8 bit and then sent to TSE_MAC. (serial PHY speed is 1.25 gbps). There is a better design to transmit payload with 1588 sync? Due to design complexity and lack of design 744 documentation, it is diffcult modify this design! Probably should more simple add data outside IEEE1588 generator/monitor but messages could be interrupted to achieve IEEE1588 synchronization.. Thanks to everyone for any help!

[SengKok_L_Intel]

Yes, understand your concern. There is no other document that guide the user to modify or customize the payload that I aware of. 

Regards -SK ​

[Ftiglius]

Thnaks! So, probably should be better to redesign own application... (!). I'm attemp to understand AN744. IEEE1588 is applied directly to ToDs: no physical clock modification are made. On this design, there is one Master Tod, and it seems distribute own sync directly to both channels 0,1. Reading about IEEE1588, an Ordinary Clock Master shold give it's syncro to Ordinary Slave via Ethernet , sending PTP messages with related timestamps, but this design seems concepted differently.... There is any possibility to obtain more infos? Thanks again for any support!