Are there specific rules about when the ready and valid signals can assert and deassert relative to each other on an Avalon Streaming Interface?

[JPate3]

This entire question is in the context of an Avalon Streaming Interface where readLatency = 0 and readAllowance = 0.

The AXI4-Stream specification explicitly states that:

• the master/source cannot wait for the slave/sink to assert ready before it (the master/source) asserts valid
• once the master/source asserts valid it must keep it asserted until the slave/sink asserts ready
• the slave/sink is permitted to deassert ready at any time

The Avalon Streaming specification doesn't seem to explicitly define the restrictions or allowances on the valid and ready signals. Are there any?

The two specific cases I am wondering about are:

1. Suppose that ready is low, is it okay for the source to assert and deassert valid, even though ready is low the whole time?
2. Suppose that valid is low, is it okay for the sink to assert and deassert ready, even though valid is low the whole time?

I realize that the behaviour of valid and ready in these cases is rather strange (as if the source and sink are changing their minds), but I'd like to know if it's allowed in Avalon Streaming. The second case is allowed in AXI4-Stream.

Thanks

[AnandRaj_S_Intel · Accepted solution]

Hi,

For readLatency = 0 and readAllowance = 0.

ready signal need to be asserted before valid data-transfer, is the only requirement.

1. Source can assert valid at any time.
2. Sink can deassert ready at any time (after that slave can't capture the data).
3. Sink captures the data from source only when ready = 1. 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)