AVALON IP LIBRARY

[RobShepherd]

Hello, I am investigating the AVALON Bus Protocol as a standard to be used in a RISC-V SoC design.

I understand AVALON to be an OPEN standard but wish to understand what AVALON IP/Macros/RTL are available for licence/purchase to support the SoC development.

Is there a simple link/URL that will show me the available IP or do I need to use a development tool to reveal the available IP library?

Thank you in advance,

Rob Shepherd

[sstrell · Accepted solution]

I don't know if this helps, but here are the Avalon specification and the Embedded Peripherals User Guide, which documents much of the IP included in Platform Designer in the Quartus Prime software for working with Avalon interfaces:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf

[RobShepherd]

Sstrell,

Thank you for this, you have saved me a number of hours searching. 

I am very grateful,

Rob

[RobShepherd]

Hello again,

(Sorry to ask)

Do you know whether the IP that is described in the guide is available in HDL form or is it a drag and drop thing that is configured and pops out from the Quartus process as a binary for programming FPGA.

The guide is named "Embedded" IP which may mean the IP is embedded in the tool only but section 41.3 (item suggests a "Generate HDL" stage but I am not sure if this applies to all items in the guide.

Please let me know if you have experience of this.

Thank you,

Rob

[EBERLAZARE_I_Intel]

Hi,

Yes, you can drag and drop and edit the IP as per the guide, and after you connect everything without any warnings/errors, you can generate the HDL.

[EBERLAZARE_I_Intel]

Hi,

The Generate HDL applies to all design in Platform Designer.