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About ALTLVDS ipcore

Altera_Forum
Honored Contributor II
741 Views

I want to use the altlvds ipcore in cycloneIII,but I have some problem about it. I used to work with hard serdes embemded in fpga(lattice ecp2m),at the receiver,it needs a input reference clk similar with the tx clk (100PPM),then the hard serdes can recovery the bit clk exactly. But in altlvds,there is soft cdr,in cycloneIII,I am not clear about the soft cdr,is it can recovery bit clk when i give it another clk which has a litter difference with the tx clk (eg.100ppm) , or at the tx port ,I need to output serial data and tx clk. then at receiver port, I use the tx clk to recovery data, which one is correct?

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Altera_Forum
Honored Contributor II
64 Views

Soft-CDR functionality isn't available for Cyclone III or Cyclone IV FPGAs. With these chips, you need a RX input clock synchronous to the data (= sourced from the TX side), not just a same frequency reference clock.

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