Now I am doing one interest thing which to test the cdr lock time of transceiver,
fpga type : arria 10 10ax115s2f45i1sg
link built : one simplex tx and one simplex rx, they use different reference clock
test pattern : prbs20
test speed : 10Gbps
test corner case : a few delay after tx starts to transmit data, set rx to locked todata and meanwhile deassert the digital reset (not the recommend tLTD in the guide), and I found that the prbs20 checker will lock quickly (about 200ns after set rx to lock data), and this value is far from the minimum value 4us in the userguide (in the userguide, it recommends to deassert the digital reset of rx after minimum 4us, and it says that after that time, the data will could be used). But from the test result, I shows that I donot need to wait so long time? Could someone provide some information about this or give me some advice to do this test?
Test wave: (yellow line : set_lockedtodata; blue line : high speed data; green line: prbs checker lock status) ; and I got about 50us time gap, the checker does not lose lock.