About when writing to reconfigure capability 0x2e0 of fPLL , there is always one recalibration once

[lambert_yu]

Hi sir/medam,

   I am facing one problem, from my simulation result wich about set pll_powerdown of fPLL through setting the 0x2e0[0] when 0x2e0[1] =1, I found one strange problem, everytime I write 0x2e0, the fPll will automatically recalibration once, I don't know  if the phenomenon is normal just because I think that fPll will recalibrate only when I write 0x1 to 0x100, could someone help me?

   software : quartus 16

   fpga chip: arria 10

Brs,

Lambert

[EngWei_O_Intel]

Hi Lambert 

In general, when you issue a pll_powerdown, recalibration shall automatically been done. The Modelsim simulation would mimic the functional behavior. In other words, what you observe in simulation will be the actual behavior in hardware. Is the fPLL for transceiver usage?

Thanks.

Eng Wei

[lambert_yu]

Hi End wei,

   Yes, I plan to use fPll for transceiver. But now I only test the fPLL reset and it's reconfig. From the transceiver PHY user guide, I believe that the calibration will occur at POR & user-mode, and at user-mode, it will occure only after we send recalibration instruction to fPLL; But from the simualtion result and debug on board, I found that every time I set 0x1 to 0x2e0[1] (pll_powerdown through the avalon-memory mapped register), there is always once recalibration before pll locks. If this action right, when I can not provide suitable reference clock to fPLL, I can only write 0x1 to 0x2e0[1] to complete recalibration and reset fPLL, but from the debug on board, fPLL didn't work. and Only do I send one recalibrate instruction to fPLL, fPll will work. So I don't know the function of the recalibration which occurs after I reset fPLL.

  Brs,

Lambert

[EngWei_O_Intel]

Hi Lambert

Can you share your simulation results?

Thanks.

Eng Wei

[lambert_yu]

Hi EngWei,

     The attahced is the simulation result(once reset through control register), you will find that pll_cal_busy is asserted and pll_locked deasserted.

     

[EngWei_O_Intel]

Hi Lambert

From your statement

"when I can not provide suitable reference clock to fPLL, I can only write 0x1 to 0x2e0[1] to complete recalibration and reset fPLL, but from the debug on board, fPLL didn't work. and Only do I send one recalibrate instruction to fPLL, fPll will work."

What do we mean by "fPLL didn't work" and "fPLL will work"? Do we mean the fPLL cannot get reset or cannot lock? The fPLL is not expected to work when you don't have a proper reference source.

From the waveform you shown, the behavior seems correct, where you have pll lock deasserted when issue a powerdown, and pll_cal_busy asserted when calibration is issued.

Thanks.

[EngWei_O_Intel]

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Eng Wei