Accessing Cyclone V SOC I/O Pins for Boundary-Scan Testing

[AINCE]

Hello,

We have Cyclone V SOC FPGA (5CSEBA6U19I7SN) and we want to test HPS pins using Boundary-Scan Test. There is a warning in the 5CSEBA6U19_HPS.bsd file as shown in attached IMAGE1. The question I want to ask, can we test HPS pins using Boundary-Scan Test? According to link shown below, we can test HPS pins using Boundary-Scan Test. But the warning in the bsdl file confused us.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd03222013_387.html

[SreekumarR_G_Intel]

Would it possible to share the bsdl file generated from the tcl console ? As of I read through the document looks it will support the hps pins via FPGA fabric.

Thank you,

Regards,

Sree

[AINCE]

Thank you for your reply,

In the attached .zip file, there are 3 bsdl files. Two of them are 5CSEBA6U19.bsd and 5CSEBA6U19_HPS.bsd and I downloaded them from the link below.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/bsdl/cyclone-v.html

5CSEBA6U19I7S_pre.bsd is generated from the Quartus II TCL Script tool.

[SreekumarR_G_Intel]

sorry for very late response ;

I looked at the HPS bsd files , i believe the warning your are getting since hps files are using the hps jtag , but as i mentioned already you have to map hps pin to FPGA fabric and use the fpga bsd file .

Kindly let me know your thought on the same ?

Thank you,

Regards,

Sree