FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6518 Discussions

Adding output signals to DSP Builder exp conduit

Altera_Forum
Honored Contributor II
1,577 Views

I need to modify the input and output signals of my DSP builder component that are available under the exp conduit in Qsys. I currently have a single bool input and a single bool output. 

 

When I add a new output in Simulink and rebuild, it doesn't show inside Qsys (I've tried bool and uint(32)). The system is updating (If I remove the existing output it no longer shows in Qsys).  

 

Is there an additional step or setting to control the input and output signals? :confused:
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
638 Views

I created a new project to test this. The signals appear to get added automatically. Something is up with my main project which is preventing new signals from showing in Qsys. I'll post an update when I figure this out.

0 Kudos
Altera_Forum
Honored Contributor II
638 Views

Solved! Not sure exactly what causes this, but you cannot use constant values as outputs in DSP builder. They must be getting optimized out. If the signal is driven by logic, it will show in Qsys when you compile and refresh.

0 Kudos
Reply