I am trying to use the XVCR Toolkit on the Atum A5 by following the user guide
SPEC:
In Section 3.7.2 the clock connections are defined:
I am using PMA clocking, with a Phase Compensation FIFO and 2x Width transfer, which implies the use of o_tx/rx_clkout2, the Word clock and a 2x division factor. Table 61 also suggests we do not need custom cadence gen.
In Section 3.9.6 the reset sequence is defined:
Which implies this snippet should be used at the top level HDL:
always @(posedge system_clk_100) begin
if (system_reset) begin
gts_i_tx_reset <= 1'b1;
gts_i_rx_reset <= 1'b1;
end else begin
if((gts_o_tx_reset_ack==1'b1) && (gts_o_rx_reset_ack==1'b1)) begin
gts_i_tx_reset <= 1'b0;
gts_i_rx_reset <= 1'b0;
end
end
end
In Section 3.11.1, the JTAG connection to the GTS is defined:
Which suggests to define the following snippet in the HPS definition:
.intel_directphy_gts_0_reconfig_address (address_bridge[17:0])
DESIGN:
All of this combines into the following GTS configuration and system definition:
GTS PMA/FEC PHY settings changed from default:
------------------------------
Datapath clocking mode : PMA
TX/RX PMA interface FIFO mode : Register
TX/RX clock clock source : Word Clock
Enable TX/RX_clkout2 port : YES
TX/RX clkout_2 clock source : Word Clock
TX/RX _clkout2 div by : 2
Enable Avalon Memory Mapped interface : YES
Enable Direct PHY soft CSR : YES
Enable Debug Ednpoint on Avalon interface : YESWith the following Qsys connections, and top level RTL connections:
module golden_top(...);
...
// GTS signals
reg gts_i_tx_reset, gts_i_rx_reset;
wire gts_o_tx_reset_ack, gts_o_rx_reset_ack;
wire gts_o_tx_clkout, gts_o_rx_clkout;
wire [79:0] gts_i_tx_parallel_data;
wire [79:0] gts_o_rx_parallel_data;
// jtag bridge
wire write_bridge, read_bridge;
wire [31:0] address_bridge;
wire [31:0] writedata_bridge;
wire [31:0] readdata_bridge;
wire [3:0] byteenable_bridge;
wire waitrequest_bridge;
wire readdatavalid_bridge;
// reset
always @(posedge system_clk_100) begin
if (system_reset) begin
gts_i_tx_reset <= 1'b1;
gts_i_rx_reset <= 1'b1;
end else begin
if((gts_o_tx_reset_ack==1'b1) && (gts_o_rx_reset_ack==1'b1)) begin
gts_i_tx_reset <= 1'b0;
gts_i_rx_reset <= 1'b0;
end
end
end
qsys_top soc_inst (
...
.intel_directphy_gts_0_i_rx_cdr_refclk_p_clk (REFCLK),
.intel_directphy_gts_0_i_tx_pll_refclk_p_clk (REFCLK),
.intel_directphy_gts_0_i_tx_reset_tx_reset (gts_i_tx_reset),
.intel_directphy_gts_0_i_rx_reset_rx_reset (gts_i_rx_reset),
.intel_directphy_gts_0_o_tx_reset_ack_tx_reset_ack (gts_o_tx_reset_ack),
.intel_directphy_gts_0_o_rx_reset_ack_rx_reset_ack (gts_o_rx_reset_ack),
.intel_directphy_gts_0_i_tx_parallel_data_i_tx_parallel_data (gts_i_tx_parallel_data),
.intel_directphy_gts_0_o_rx_parallel_data_o_rx_parallel_data (gts_o_rx_parallel_data),
.intel_directphy_gts_0_reconfig_write (write_bridge),
.intel_directphy_gts_0_reconfig_read (read_bridge),
.intel_directphy_gts_0_reconfig_address (address_bridge[17:0]),
.intel_directphy_gts_0_reconfig_byteenable (byteenable_bridge),
.intel_directphy_gts_0_reconfig_writedata (writedata_bridge),
.intel_directphy_gts_0_reconfig_readdata (readdata_bridge),
.intel_directphy_gts_0_reconfig_waitrequest (waitrequest_bridge),
.intel_directphy_gts_0_reconfig_readdatavalid (readdatavalid_bridge),
.gts_jtag_master_0_master_address (address_bridge),
.gts_jtag_master_0_master_readdata (readdata_bridge),
.gts_jtag_master_0_master_read (read_bridge),
.gts_jtag_master_0_master_write (write_bridge),
.gts_jtag_master_0_master_writedata (writedata_bridge),
.gts_jtag_master_0_master_waitrequest (waitrequest_bridge),
.gts_jtag_master_0_master_readdatavalid (readdatavalid_bridge),
.gts_jtag_master_0_master_byteenable (byteenable_bridge),
...
);
...
endmodule
The boot output:
TFTP from server **bleep**.**bleep**.xx.x; our IP address is **bleep**.**bleep**.xx.x
Filename 'fpga/soc_system_base.rbf'.
Load address: 0x90000000
Loading: #################################################################
#################################################################
#########
2 MiB/s
done
Bytes transferred = 2031616 (1f0000 hex)
...
FPGA reconfiguration failed!Command 'load' failed: Error -110
FPGA not ready. Bridge reset aborted!
Did I overlook something? Any help would be greatly appreciated!
Many thanks!
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