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Valued Contributor III
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Altddio - rgmii

Hi, 

I'm preparing design on Cyclone V with RGMII connection. I read AN 477 ("Designing RGMII Interfaces with FPGAs and HardCopy ASICs") about it and I understand what is necessary to do. I miss only one major information. It is necessary to use DQ/DQS pins on FPGA for TXD and RXD pins? 

Thanks, 

Milan
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Valued Contributor III
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I believe it should work with regular DDR I/O. (Cyclone V and 28nm is getting slow enough with source-synch I/O that it's not a slam dunk, but I believe I've seen it done.)

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Valued Contributor III
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OK, I can connect RX and TX data on DQ pins but how about RX_CLK and TX_CLK? Has they be connected on dedicated CLK pin or on the DQS pin? I can imagine, that the receive clock is on DQS pin and transmit clock is on dedicated CLK pin, but I'm not sure that it is right solution.

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