FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Altera Dual Port RAM

Honored Contributor II

Hi Guys, 


I've written a program in VHDL to access CIS and get data and transfer the data over USB using cypress USB transceiver CY7C68013A. 


CIS : 1728 Pixels/Line, Output in three parts of 576 bytes.  

CIS clock speed : 6.25Mhz, Max 8 Mhz. 


FPGA : Cyclone III-EP3C25Q240C8N. 


ADC : AD9200, 1st sample appears on the 5th clock hence first 4 clocks cycles are skipped for every line read. 


Am using altera Dual Port RAM to get datas from the three outputs simultaneously and storing the datas in to 3 DPRAMs once this operation is done then I read the datas from DPRAM sequentially 1, 2, 3 and write the datas into cypress USB transceiver. 



When the image is created in the GUI, last four bytes (573,74,75,76) of the output is shifted to the first four bytes(1, 2, 3, 4). This four byte shift happens in all the three outputs.  


I couldn't figure out what is the problem in my code. 


Please Help. Thanks in advance.
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Honored Contributor II

your problem needs simulation to find out where data is shifted. It is several stages and I wouldn't suspect the ram to do that.

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