FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

Three Wire SPI connection question

Why can't EP4CGX15/22/30 support HD-SDI?

tse_mac that compiled/worked in 10.0 erroring out in 10.1

PATA to SATA Conversion IP core

audio core

Problem simulating DDR2 SDRAM Controller with ModelSim

wrong data through IFFT, FFT

How to add BFM design file in project containg IP core

DSP builder install problems. HELP

HW PCIe with GXBL1

uart_16550 Loopback Test

Ddr2 hp

Need better understanding of HPC/DDR usage

9.1 Avalon OpenCores 10/100 Ethernet MAC with DM9000A

does lpm_mult,lpm_adder,lpm_rom need license

Featured Content

dynamic configuration issue of fpll from arria 10

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)