FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

fir compiler: "actual coefficients" or "bit width only"? scaling and SNR relationship

MAC address at receive Tripple Speed Ethernet

read problem with DDR2 HP II controller

ALT2GXB rx_pll_locked

PCI Express Tx interface gets stalled

Problem with DDR SDRAM controller (words swapped)

Design protection with external security device

Questions about DMA

PCI system with DMA

Nios II address range issue

Avalon Video Streaming Protocol: Control Data packets

It cannot show any blocks about Altera DSP Builder Blockset in the matlab simulink

IVP suit scaler problem

Ethernet MAC/PHY (LAN91C111) with Stratix II

Kit DSP Development STARTIX II Profesional Edition

Featured Content

UART Core IP (RS-232 Serial Port)

Can a 1000mbps RGMII TSE communicate with a 100mbps PC?

Critical Warning: PLL clock

Re: Can a 1000mbps RGMII TSE communicate with a 100mbps PC?

Re: Can a 1000mbps RGMII TSE communicate with a 100mbps PC?

Error reported by S-function 'mip_control' in Control Block

Re: Altera Simple Dual Port RAM -- Read cycle latency