FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Altera LVDS serdes IP

Honored Contributor II

Hi all, 

do you know if somewhere design with LVDS receiver for serial LVDS A/D converter ?  

I plan use AD9653, where i connect to fpga DCO+- (data clock), but i donť know, what i can use with FCO+- (frame clock) ? 


Thank you for answer. 


Jan Naceradsky, Czech republic
0 Kudos
1 Reply
Honored Contributor II

You're best off ignoring the data clock, and using the frame clock. Use the ALTLVDS core and set it up so that the input clock frequency is that of your frame clock. 


The data clock contains only information about each bit period. The frame clock contains information about both the bit period (it's frequency is exactly bit rate / number of bits), and the word alignment. The PLL instantiated by the ALTLVDS core can multiply the frame clock to recover the data clock and use the frame clock to correctly align data words in the output.
0 Kudos