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IOzan
Beginner
472 Views

Altera PLL is not working

Hi,

I'm trying to implement the Altera PLL from the IP catalog and no matter what I do- this simple cure is not working! (outclk_0 is constantly red signal in ModelSim). I'm working with Quartus Prime Lite Edition 17.1, ModelSim 10.5b and 5CEFA7F31I7 Cyclone V FPGA (EVM).

My ref clock is 50MHz and the desired and the actual is 48MHz. The other parameters are default (Direct, Integer-N PLL, Phase shift 0ps, D.C=50%, with locked output signal and input reset signal (active high but I even tried to toggle is in 1Hz).

What could possibly be the cause for the standard PLL cure???

Help…

Idan

  

 

 

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6 Replies
AnandRaj_S_Intel
Employee
187 Views

Hi Idan,

 

  1. Have you applied reset?

Try applying reset and given appropriate inputs to get the expected output.

 

Regards

Anand

IOzan
Beginner
187 Views

 

Hi,

I did… as I mentioned, I even toggle the reset at 1Hz. The ref clk is always present at the input signal.

What else can I do to operate the PLL cure?

Help…

Idan

AnandRaj_S_Intel
Employee
187 Views

Hi Idan,

 

Are you using just PLL IP stand-alone or initiating PLL IP on top-level HDL for simulation? Check the connectivity of the ports or pins.

 

Try after deleting the work folder from the simulation directory.

 

Attached some images.

 

Regards

Anand

IOzan
Beginner
187 Views

Hi,

Here are some snap shots from my code and simulation (and I'm attaching the project itself). 

Help...

Idan

IOzan
Beginner
187 Views

And the complete code that is not working (PLL output is all red (U)).

What can I do to make it work?

Can you try to run the code in your Quartus and ModelSim versions?

Thanks,

Idan

AnandRaj_S_Intel
Employee
187 Views

Hi Idan,

 

Your design looks good, You have to recheck the simulation steps. Please read msim_setup.tcl(Simple_counter_PLLC\Filter_PLL_C_sim\mentor) file which will help in simulation step if you have top level file.

I have attached the modelsim transcript and image. save below code as mentor.do and run

set QSYS_SIMDIR C:/<Directory>/Simple_counter_PLLC/Filter_PLL_C_sim source $QSYS_SIMDIR/mentor/msim_setup.tcl   dev_com set TOP_LEVEL_NAME tb_Simple_counter elab

Regards

Anand

pllsim.JPG

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