I currently have a Cyclone 10 GX and I was testing the XCVR_NativePhy IP and the XCVR_ATXPLL IP. I succeeded in setting up a Basic (Enhanced PCS) transceiver at 10400 Mbps with a 64 bit wide PCS/PMA interface and a ATX PLL with an output frequency of 5200 MHz. I succeeded in transmitting the data and receiving it correctly. I wanted to have the data rate at 10000 Mbps and a PCS/PMA interface width of 100 bits. The options for that width do not exist. Do I need to create a custom IP? How would I go about doing that? Is this possible?
From transceiver serializer/de-serializer architecture perspective, the max PCS/PMA is 64 bits. There is no way to go beyond that.
My suggestion is you need to post process the data accordingly in FPGA core logic using your own custom IP.
Thank you very much for responding!
That is what I was afraid of. Are you suggesting that I maybe use a 20 bit wide interface and then some type of state machine to step through all 100 bits of my desired data packet? Would it then take 5 times as long to send the same data or would I simply have to step through the state machine 5 times faster to supply the transceiver with the data at the desired rate?
Yup, you got it right. It will take 5 times longer to sample all 100 bits.
Are you building custom protocol or follow some industry standard protocol.
Industry standard protocol typically has fixed the transceiver data rate so user can't simply boost the data rate
I am doing a custom interface. When I was testing the 10.4 Gbps with a 64 bit wide PCS/PMA interface, I was clocking the parallel data in at 162.5MHz which gave me the 10.4 Gbps constant stream (I want a constant stream of data). If I will now be running at 10 Gbps with only 20 bit wide PCS/PMA does the transceiver handle clocking the parallel data in at 500 MHz so I can get all 100 bits into the desired 10nS span for a constant stream of data?
Thank you very much for taking the time to help me understand all this, this is my first foray into multi-gigabit transceivers.
There is one thing I am still confused on if you don't mind explaining or at least pointing me in the right direction so I can learn about it.
If I wasn't trying to allocate every possible bit (5 frames of 20 parallel bits at 500MHz for a 10GHz serial stream of 100 bits every 10nS), what does the transceiver do if I were only sending 2 frames of 20 bits? How do I choose what frequency to clock the 20 parallel lines into the transceiver at? What does the transmitted signal look like in between frames?
Are you trying to confuse yourself and me ? :)
Let's revisit the basic again. Below statement is TRUE regardless of whether there is data traffic or not
The transceiver channel is just a physical medium to pass through the data at some desired speed. It doesn't process or manipulate the data. That's the job of user core logic design
Some of the important notes :