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Valued Contributor III
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Altsyncram mixed port width issue

Hi, 

Having problems generating a simple mixed dual port RAM using M10 block memory. Using Quartus 16.1.0 Build 196, for CycloneV SX (5CSXFC6D6F31C6) FPGA. Trying to generate an Oncip Memory RAM in QSys with the parameters shown on the image. https://alteraforum.com/forum/attachment.php?attachmentid=14714&stc=1  

 

Compiling the generated files produces the following error (at Analysis and Elaboration stage): 

Error (272006): Cannot use port A width with port B width in altsyncram megafunction 

Error (287078): Assertion error: The current megafunction is configured for use with the clear box feature and cannot be used when the clear box feature is disabled 

 

PortA width is 64 bits, PortB width is 256 (i.e. mixed width ratio is 4). According to Embedded Memory User Guide (and the Megawizzard Manager itself) this is a valid combination of mixed-width. To be specific, ug-01068 | 2017.11.06, 3.5 Mixed-width Ratio Configuration: for True Dual Port Memory without Byte enable valid ratios are 1, 2, 4, 8, and 16. 

What is wrong?
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Valued Contributor III
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Re: Altsyncram mixed port width issue

The table in that doc is for Arria 10. You should check the Cyclone V device handbook for the supported ratios.

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Valued Contributor III
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Re: Altsyncram mixed port width issue

ssterll, you right, I've noticed that the table is for Arria 10 afterwards. But it is not the main point. And, by the way, Cyclone V Handbook refers back to ug_ram_rom.pdf. I.e. in "Mixed-Width Port Configuration" section it states the following 

 

--- Quote Start ---  

embedded memory (ram: 1-port, ram:2-port, rom: 1-port, and rom: 2-port) user guide (http://www.altera.com/literature/ug/ug_ram_rom.pdf) Provides more information about dual-port mixed width support. 

--- Quote End ---  

 

There is also a table "M10K Block Mixed-Width Configurations in True Dual-Port Mode", which sort provides the answer, but not quite. It only gives the ratios for 1-32 (40) bit wide buses (just for individual M10 block, not abstract "memory"), whereas I am interested in 64-256 bit wide buses. One would suggest, that wider buses are implemented by dividing into smaller chunks, best suitable for multiple M10K blocks. 

 

I should also point out, that the memory is instantiated as a part of QSys system. I.e. the picture with parameters in the original message is for "On-Chip Memory (RAM or ROM)" component, used as a part of QSys system. Here the combination of PortA Width=64, PortB Width=256 is valid. But, if I try to use IP-Megafunction (outside of QSys) "Onchip Memory: RAM: 2 port)", it doesn't even allow buses wider than 128-bits! 

 

So I still have the following questions: 

1) What are the possible combinations for CycloneV mixed-port memories in general? And specifically, for PortA=64, PortB=256 combination, is it a valid one? 

2) Whatever the answer to the 1'st question, QSys allows to use (invalid?) parameters for onchip memory, which lead to errors during compilation (Analysis & Elaboration stage).
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Valued Contributor III
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Re: Altsyncram mixed port width issue

I had same issues with u when use Qsys, mem 2 port, porta 32bits, portb 8bits. (synthesis false). 

Error (272006): Cannot use port A width with port B width in altsyncram megafunction 

Error (287078): Assertion error: The current megafunction is configured for use with the clear box feature and cannot be used when the clear box feature is disabled 

Compared with file generate from IP Catalog, with same config. (systhesis ok). I figured out that issue was 

 

.byteena_a(byteenable) 

then I changed it to .byteena_a(4'b1111) // in this case, I use full 4byte for port a 

 

It okayed with me.
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Beginner
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Re: Altsyncram mixed port width issue

Hi, I met the same question like you. But I do not know where to find the  .byteena_a(byteenable) , would you like to tell me some details? thanks a lot!

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