I'm having trouble implementing the example project generated when instantiating a DDR2 interace on a Cyclone V device on a custom board. At this point, I am trying to create a soft memory interface (saw a note that the EMIF doesn't work with hard memory interface, don't know how accurate that is) running at 300 MHz on a custom board to connect to . It appears the timing closes at this point, and I've entered what I believe are correct values for the memory device timing parameters and my board parameters, but I still always get a failure in the calibration at the guaranteed read stage on group 0.
I was able to generate an example DDR3 interface on the Cyclone V E development kit and get it to pass the driver test, and I am trying to recreate the same overall structure on my board (PLL, ISSP, DDR2 interface and DDR2 driver created by MegaWizard).
I'm at a bit of a loss as to what to try next to get this module working, so does anyone have any thoughts as to what to try next? I can upload some SignalTap or other debugging outputs if anything would be particularly useful.
There are multiple reasons that may cause DDR2 calibration failure.
For a start, you can check below EMIF spec estimator link to ensure the DDR2 selection is not out of spec.
After that, you review attached debug checklist to get some debug idea as well.
Thanks for the reply. I have verified that the DDR2 selection is not out of spec for the EMIF. At this point, I am working my way through the debug checklist, but am having trouble with the board skew parameter estimator. I will be out of the office for a week but will get back to you with those results when I can.
I have seen some confusing and/or conflicting information about termination for the DDR2 interface on the Cyclone - do I need a 100ohm resister to ground from the oct_rzqin pin? What is the default termination on the interface?
Thanks for the confirmation. I omitted this resistor in the initial design but have had our techs try to add it to the board. Its possible that the wiring wasn't quite done right - what kind of failure would you expect without this termination resistor connected to GND?
Also, does changing the current setting for each of the pins alter the termination resistance? I know the default example design sets the memory interface to MAXIMUM CURRENT, but would changing this setting improve the match to the memory device?
Rzq is the termination resistor reference used for IO standard calibration. Wrong termination resistor will end up with wrong calibration result and hence hurt the signal quality potentially leading to DDR2 write/read failure.
Current setting is used to tuned the signal quality as well. You need to run board simulation to find the optimize setting that suit your board design. Else you can just stick with the default setting for now.
I've worked on this quite a bit and am still having calibration failures on the guaranteed read step on group 0. At this point, I have worked through the board skew parameters worksheet to determine and input the correct board skew parameters, I've closed the timing, and performed simulations to verify my board-level terminations, and I'm still getting calibration failures.
What would you recommend as a next step to testing this design and hopefully getting it to work? Is there anything else I can do to determine whether or not its a board-level issue or one with my vhdl?
Assume you have key in all the correct DDR2 setting in DDR2 IP, then the easiest way to debug is to use DDR2 example design generated from DDR2 IP.
If example design passed - then most likely is your board design issue
If example design failed - then it could be DDR2 IP setting or board design issue.
What I'm trying to get to work right now if the example design very slightly modified to fit a custom board (just routing the signals correctly and adding a few output signals). So the example design is failing and I'm trying to narrow down whether these are board or IP settings issues. Any suggestions how to best figure this out?