I am working in ARRIA 10 GX development kit for testing the PCie end point protocol.I have configured the pcie end point IP for X1 lane and generated example design for that configured IP.
Given pin assignment and compiled the design with generated .SOF file.Programmed the .SOF file in development Board and detected the Pcie device ID in the host pc using RW everything tool.Detection is working fine.
My aim is to send the data from Pcie end point to root complex(host PC).For that I have taken the TX_ST_data,TX_ST_VALID in the signal tap analyser to see the data generated from the example design, but i didnt get any data from that signal. It is showing Zero in that signal.
Why this example design is not giving any tx_st_data?It should give some data in that signal...