Arria 10 IOPLL not locking when reconfiguring

[CHebl]

Hi all,

I'm currently trying to reconfigure an IOPLL with the Reconfiguration IP-Core by accessing the registers of the Core.
The PLL has been configured to run with an 80 MHz input clock and 240 MHz output clock and locks.
The goal is to reconfigure the output to 80 MHz.
The sequence in doing so is the following:

1. Take parameters for reconfiguration from QSYS
2. Write M Register (0x90)
3. Write N Register (0xA0)
[3.1] Write 0 to address 0
4. Write C Registers (0xC0 and further)
[4.1] Write 0 to address 0 after each C Register change
5. Write Charge Pump (0x20) register
6. Write Loop Filter (0x40) register
7. Write 0 to address 0

Steps in brackets are optional. It didn't make a difference executing these steps or not doing them.

I'm currently observing the PLL not being able to lock at all (configured the IOPLL reconfiguration core with parameter WAIT_LOCKED = 0 to not hang my watchdog timer).
The output clock, when configured to 80 MHz jitters in between 70 and 80 MHz.
The input clock is stable 80 MHz. Simulaton of the whole system works as expected.
Reading back the written registers provides the exact values I've written.
I'm currently using Quartus Prime 20.1.1 Standard edition

Are there any bugs to be aware of and is there a solution to make the reconfiguration work? Many thanks for your help.

[Ash_R_Intel]

Hi,

I am guessing that you are following AN 728.

You need not write 0 to address 0 after every write command. It is required at the end of the steps. This is not so problem creating step though.

It is important that you refer the Design Considerations mentioned on page 13.

Are you applying reset to the PLL? Is the design meeting the timing?

Regards.

[CHebl]

Hi @Ash_R_Intel ,

I am following AN 728 and applying the avalon reset of the IOPLL after reconfiguration (asserting for 1 ms and waiting for 1 ms until evaluating lock).
Also I write 0 to address 0 after each command now.

Lock goes high for 722 clock cycles (measured with signaltap, 100 MHz -> 7.22 us) before going low again.
Timing is met for 240 MHz output clock and for 240 MHz the PLL locks without trouble (without reconfiguration). After reconfiguration with the same values that the PLL is initially configured with results in a loss of lock. The PLL is configured in direct mode. Changing this to normal or source-snychronous didn't change the behaviour either.

Many thanks for your help

[CHebl · Accepted solution]

Hi @Ash_R_Intel ,

I just found, that I made an programming error and didn't configure the Loop Filter correctly. PLL is now locking. Many thanks for your patience and help.

[Ash_R_Intel]

Glad to know that you found the issue!!

Let us know if you need any other help. Closing this case for now.

Regards