Arria 10 Native PHY dynamic reconfiguration with embedded streamer, standard/enhanced PCS and TX PLL switching design example

[PTan9]

Dears,

I want to request below example design files in Design Store beacuse the original link is invalid in Design store. Thanks.

Arria 10 Native PHY dynamic reconfiguration with embedded streamer, standard/enhanced PCS and TX PLL switching design example  

Best Regards

Penn

[Nathan_R_Intel]

Hie,

The old design is currently not available. However, the description of the design, its connection and the IP parameters editor configuration is described in the following youtube link.

https://www.youtube.com/watch?v=6ykKfqLCho4

Hence, you could re-create the design in latest Quartus version using the youtube link.

Regards,

Nathan

[PTan9]

Dear Nathan,

I have checked the video. The video just show how to perform data rate change of standard PCS using TX PLL switching and embedded streamer in Arria 10 transceiver. I want to know how to perform protocol change between GE, 10GE and 5G basic by enhance PCS of Arria 10 transceiver using the embedded streamer in TX PLL(TX PLL support embedded streamer afterQuartus 16.1) and Arria 10 transceiver. Do you have any materials and suggestion for reference? Thanks.

Best Regards

Penn

[Nathan_R_Intel]

Penn,

The youtube design shows the building blocks of the design used to perform Tx PLL switching using embedded streamer in Arria 10 transceiver. Anyway please refer to the Dynamic Reconfiguration Chapter 6 in the Arria 10 Transceiver Phy User Guide to understand about dynamic reconfiguration of the transceiver.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

However, it seems your request is to perform protocol change betwee GE, 10GE and 5G. Currently, for Arria 10 dynamic reconfiguration of transceiver is mainly supported through Native Phy IP. However, using Native Phy, you can only reconfigure the PMA and PCS. The method is to generate multiple reconfiguration profiles for 1G,5G and 10G using Native Phy. Then you can use the embedded streamer to load the mif content to dynamically change the PMA, PLL configuration and switch between standard PCS and enhanced PCS. The timing diagram for embedded reconfiguration streamer is shown in Figure 274 of the user guide to describe which register to read/write to use the embedded reconfiguration streamer. Also, the steps to perform dynamic reconfiguration is on Pg524.

Alternatively, to really switch between GE/10G and 5G ethernet, I will recommend to use Multirate Ethernet Phy IP, which enables additional features using soft logic in fabric (ex: Auto-Negotiation). Besides, the Multirate Ethernet Phy IP also has a Generate Example design feature which allows you to generate the example design and use it directly. please refer to the following user guide for details:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20016.pdf

Regards,

Nathan