Arria 10 PCIe, wrong frequency in the timing analyzer.

[sl242]

Hi,

We are using the Hard PCIe in Arria 10 with Hard IP mode is set to "Gen3 x2, Interface 128bit, 125 MHz". The communication works fine, but the coreclkout_hip frequency is not displayed correctly in the timing analyzer.

Frequency expected: 125MHz
Frequency measured: 125MHz
Frequency reported: 156.25MHz

Since the frequency is reported too high, the timing analyzer reports an incorrect timing violation.

The coreclkout_hip is reported as "u0|sys_pcie|sys_pcie|wys~CORE_CLK_OUT" see attached images.

Quartus Prime Version 22.3.0

Best Regards

[FvM]

Hi,
timing analyzer isn't responsible for "wrong" clock frequency, it's only reporting clocks specified in your design.
I agree that hip_coreclock should be 125 MHz, question is how you managed to get 156 MHz in your design. How was the design created, is it based on PCIe AVMM endpoint design example?

[sl242]

Hi FvM

I have taken over this project, so I don't know on what basis it was created. I suspect it is from scratch. I made some unrelated changes to the parameters of a clock bridge and the problem has disappeared. I will come back if the problem reoccurs.

Best Regards

[KhaiChein_Y_Intel]

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. 

If you have a new question, feel free to open a new thread to get the support from Intel experts.

Otherwise, the community users will continue to help you on this thread. 

Thank you.

Best regards,

Khai