How to see TLPs on the Rx Streaming interface

[binupr]

Hi there,

We are checking TLP transactions on the Rx streaming interface of the Intel Agilex Ptile based SoC. What is the bare minimum needed to see TLP packets going through the RX streaming interface of the Intel PCIe IP? Configuration used is Gen 3, 2x8 EP and using the provided example design by Intel.

• Does the simple enumeration propagate TLPs to the Rx streaming interface or does these configuration TLPs get terminated at the controller itself?
• Have signal tap probing the RX streaming interface of the Intel example design see. I can see the ready signal (input to the controller from application interface) is asserted high but no TLPs coming through even when we try to write to register space via 'setpci' command.

We do not see any errors (TLP abort/malformed TLPs etc) so it is very puzzling. Link is up- so definitely makes me think that the data link layer is working but for some reason the transaction layer is not getting activated.

Any clues on this is much appreciated.

Thanks

BPR

[Chris039]

Can you share the signal tap for the signaling behavior?

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question. This thread will be transitioned to community support. 

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Best regards,

Khai