I am looking into Arria 10 FPGAs and the HMC soft controller.
I am refering to these documents:
Intel® Arria® 10 Transceiver PHY User Guide (d2pgu9s4sfmw1s.cloudfront.net)
Hybrid Memory Cube Controller IP Core User Guide (mouser.com)
It seems like for a full-width HMC controller (i.e. a 512-bit user interface), 16 lanes (or channels) are required. But the full-width controller also supports multiple ports (up to 4).
If we use 4 ports with a full-width HMC, that means we can get 4*512 bits = 2048 bits per clock at the user interface, right?
If we use 4 ports with a full-width HMC controller, does that mean 16*4 = 64 lanes will be required? Or does it still only need 16 lanes, irrespective of the number of ports?
I know HMC is not used any more, but I am mostly just looking into the DRAM bandwidth (at the user interface) that is possible on such devices.
Thanks in advance for any guidance.
