Atari XL nostalgia: delayed output line from 1.77MHz clock input

[HDele]

I rediscovered my old Atari 600XL in the attic. The resurrection failed because the "delay line" (a chip that inputs 1.77 MHz and outputs 5 clock signals at the same frequency in different delays) did not pass the test of time.

The 5 output pins delay the input clock by 25, 190, 260, 315, 440 ns.

Tolerances of 20ns should be allowed. 

How can I realize a simulation using my DE0-nano (50Mhz)?

Thanks for support.

Holger

[Rahul_S_Intel1]

Hi,

From your question, I interpret that you need an clock output source from an input source with a delay.

If you are using DE0-nano,

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=593

Requesting to use an pll to generate the above configuration