Audio Extract MegaCore

[Altera_Forum]

Hello, 

we are planning to buy Audio Extract core for audio extraction from SDI signal. The datasheet says, that the output is 12S/AES. Is there a mistake and it is possible to get I2S audio output, because it is exactly what we need.  Thanks.

[Altera_Forum]

i'm sure that must be a typo and its meant to say I2S 

 on the other hand that is the only reference to I2S in the documentation. on page 93 of the SDI UG, it says the SDI cores use the AES standard, so i'm not sure why the document shows I2S as well. you might file an SR to get clarification  i don't think converting AES to I2S should be too tough if that's where you end up

[Altera_Forum]

Since it is impossible to test, I am confused if it is possible to switch the output format. I understand, that UG means user guide, but what SR means? :)

[Altera_Forum]

SR is Service Request filed at the mySupport section of altera.com

[Altera_Forum]

Thanks. I will inform about the answer here.

[Altera_Forum]

No reply from Altera yet (great support guys!) 

 However, I am still trying to implement audio extraction, but it doesn't work. I provide the audio extract core with vid_data, vid_clk, vid_data_valid signals (manual table 4-10), but no output is available. Since I don't need RAM, error or any other status/control/etc registers, I don't use reg_clk input to provide clock to that input. The "include clock" option is also off, so I don't use fix_clk signal, because there are no fee PLLs left for 200MHz clock. This means, that I have to use aud_clk signal feeding it with 3.072MHz signal. However, when all resets are tied to 0, all video signals are OK and 3.072MHz is provided, there are no output signals. What did I forget?

[Altera_Forum]

I will respond to my thread once again, for people facing same problems in the future. 

 The audio extract and audio embed cores both support I2S, AES and parallel input audio (I've managed to find out that myself). It is better to use fix_clk option, but if You have 3.072MHz clock signal + data sync to video - both cores works without fix_clk. reg_clk signals can be left unconnected, if You don't use status and control registers.  Those new schematic symbols for both cores are weird and it is hard to understand which pin is input and which is output.  Altera didn't bother to respond to service request yet :)

[Altera_Forum]

Hi Socrates 

 May I ask you a question about the output of SDI extractor?  The SDI extractor has three outputs - aud_ws, aud_data, aud_clk_out. Are these three signals I2S signals? (I've searched keyword I2S in SDI user guide and cannot find it) If so, I think I can set these three signals as output pins and connect to some audio processing IC.  Thanks.

[Altera_Forum]

Yes. 

I2S is not mentioned in the datasheet because Altera didn't make this core. It was developed by a 3rd party company and later sold to Altera afaik.

[Altera_Forum]

Do you know about the source?

[Altera_Forum]

--- Quote Start ---  I will respond to my thread once again, for people facing same problems in the future.  The audio extract and audio embed cores both support I2S, AES and parallel input audio (I've managed to find out that myself). It is better to use fix_clk option, but if You have 3.072MHz clock signal + data sync to video - both cores works without fix_clk. reg_clk signals can be left unconnected, if You don't use status and control registers.  Those new schematic symbols for both cores are weird and it is hard to understand which pin is input and which is output.  Altera didn't bother to respond to service request yet :)  --- Quote End ---   Did Altera finally responded to SR? If Yes, then what was the answer? Did You finally managed to make it work?

[Altera_Forum]

Can Audio Extract IP core extract audio data from any BT656 or BT1120 video streams with embedded audio or it only works within Altera SDI IP core? 

Can Audio Embed IP core embed audio data into any BT656 or BT1120 video streams or it only works within Altera SDI IP core?

[Altera_Forum]

SDI core and audio embed/extract cores are separate. Since SDI core will give/take BT656 on output, it means, that You can use audio embed/extract on any BT656 stream You have. 

 P.S. or BT1120.

[Altera_Forum]

What is AES Output Module in the Audio Extract IP Megacore which supposed to transform "internal AES" to "real AES" output as seen at the attached image from Serial Digital Interface (SDI) MegaCore Function User Guide? 

https://www.alteraforum.com/forum/attachment.php?attachmentid=7511

[Altera_Forum]

--- Quote Start ---  Yes. I2S is not mentioned in the datasheet because Altera didn't make this core. It was developed by a 3rd party company and later sold to Altera afaik.  --- Quote End ---   Do You mean, that it was developed by Omnitek?

[Altera_Forum]

Don't remember which company it was... And probably doesn't make any difference now? :)

[Altera_Forum]

Yes, it is Omnitek.  

Their Audio Embed / Extract IP is identical to Altera's.  Omnitek's Audio Embed / Extract IP has I2S or AES selection settings and has some minor differences from Altera's.

[Altera_Forum]

--- Quote Start ---  Hi Socrates  May I ask you a question about the output of SDI extractor?  The SDI extractor has three outputs - aud_ws, aud_data, aud_clk_out. Are these three signals I2S signals? (I've searched keyword I2S in SDI user guide and cannot find it) If so, I think I can set these three signals as output pins and connect to some audio processing IC.  Thanks.  --- Quote End ---   Hi, YUFU0511 and Socrates! SDI Audio Extractor has not only aud_clk_out ( which is an output ), but also aud_clk ( which is an input ). Both are described as being 3.072 MHz. How to deal with that? Where from do I have to take 3.072 MHz to feed to aud_clk input? From aud_clk_out output? Does that mean, that I have to connect aud_clk_out to aud_clk input? It seems strange, that Audio Extractor may need anything else besides input video signals.  Did You try connecting aud_ws, aud_data, aud_clk_out to I2S inputs of any audio processing IC? If Yes, the does it really recognize them as I2S ?

[Altera_Forum]

Is it possible to access SDI Audio Embedder / Extractor IP Cores by NIOS II if Audio Embedder / Extractor IP Cores are connected to NIOS II in QSYS via Avalon Memory Mapped Interface? 

If Yes, then please point me where can I find an example or please show Your own example in this thread.

[Altera_Forum]

--- Quote Start ---  Hi, YUFU0511 and Socrates! SDI Audio Extractor has not only aud_clk_out ( which is an output ), but also aud_clk ( which is an input ). Both are described as being 3.072 MHz. How to deal with that? Where from do I have to take 3.072 MHz to feed to aud_clk input? From aud_clk_out output? Does that mean, that I have to connect aud_clk_out to aud_clk input? It seems strange, that Audio Extractor may need anything else besides input video signals.  Did You try connecting aud_ws, aud_data, aud_clk_out to I2S inputs of any audio processing IC? If Yes, the does it really recognize them as I2S ?  --- Quote End ---    Hi, Aphraton,  About the connection question, you may see an example design for audio extractor. (The example design can be found in the folder xxx/altera/(your quartus II verions)/ip/altera/audio_embed/example/)  For your second question, in my case, I extract AES audio and write my own module to convert the AES audio to I2S signal.

[Altera_Forum]

--- Quote Start ---   For your second question, in my case, I extract AES audio and write my own module to convert the AES audio to I2S signal.  --- Quote End ---   Does that mean, that extracted set of signals aud_ws, aud_data, aud_clk_out is not according to I2S as it was earlier said by Socrates?