I've been using Cyclone V device that communicates with a host PC via
PCI Express. The communication logic is built using Qsys "Avalon-MM
Cyclone V Hard IP for PCI Express". On the host PC (x86-64),
CentOS 6.x (Linux kernel 2.6.x) is running. The system has been working fine
for more than a year without problem.
Recently, however, I noticed that the DMA write (memory write
initiated by the device) does not work properly on CentOS 7.x (kernel
3.10.x). Note that other functions including PCI configuration read/write and
the host initiated memory read/write are working fine. DMA read is not
implemented and thus not tested.
Looking inside the status register of Qsys DMA Controller, I found that the
bit1 remains high forever, which means DMA is started but never completes.
I am sure the following registers are properly set before starting the
DMA. The value of address 03h (length register) does not decrement at
all, even a few minutes after the kicking off of the DMA.
01h readaddress RW start address of a read.
02h writeaddress RW start address of a write.
03h length RW length in bytes. decrements to 0 as the transfer proceeds.
06h control RW
So my question is: what can make the DMA controller busy forever?
If a wrong value is set to 02h (writeaddress), could that
cause the DMA controller behave like this?
Please help. Any idea or suggestion would be greatly appreciated.
