FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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6162 Discussions

is it possible to transmit 1080p30 using the SDI II IP core?

Honored Contributor II

I am using the SDI II IP core in triple-rate (SD/HD/3G) transmitter mode with a 148.35 MHz reference clock. Video timing is generated by a clocked video out IP core . When I set the tx_std input of the SDI transmitter to “011” (3G level A) and select 1080p60 timing preset in the CVO module, everything works as expected. I am now trying to figure out how to put out HD-SDI (1080p30) instead of 1080p60. Does anyone know how I can do this? It doesn’t seem to be as simple as setting the tx_std input to he SDI II module to “001” (HD-SDI) mode. I’m guessing that I have to also throttle the CVO somehow, but I’m not sure how to do this. It doesn’t have a 1080p30 preset, and doesn’t seem to have any enable or backpressure controls. Is 1080p30 even possible ? 


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Honored Contributor II

The example design will tell how to transmit HD-SDI data to the SDI II IP Core. I think the data valid could be 1 high and 1 low to make the parallel data band width 50% against 3G-SDI. BTW, the reference clock would be 148.5 MHz if you want to transmit 30 or 60 fps video format.