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Avalon-ST on Intel PCIe IP

DNguy4
Beginner
837 Views

Hi,

I am using the Avalon-ST interface in my FPGA for streaming application. Most of the time, I will be sending data from host to FPGA. Memory write appears to be the right command for this task. However, I can only write 32 or 64 bits per tlp depending on the data width of my BAR. This is very inefficient since 50% of the tlp is the header.

Is there a better way to do it?

Intel/PCIe recommend not to use IO read/write for new design.

Thanks in advance

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4 Replies
GuaBin_N_Intel
Employee
113 Views
Could you specify which device and IP are you referring to?
DNguy4
Beginner
113 Views

I am using Arria10 10AS066H3F34I2SG and the IP is Intel Arria10/ Cyclone10 Hard IP for PCI Express with Avalon-ST interface.

AndyN
New Contributor I
113 Views

Your problem is probably on the host software side. How are you commanding the write? Are you sure that it is actually trying to move more than 64 bits in one operation? The IP is definitely capable of receiving an awful lot more than that but it's quite easy (speaking from experience) to have the software-side PCIe driver not actually do what you expected...

DNguy4
Beginner
113 Views

I agree. It looks like the problem is on the host SW but we can't figure out yet.

We are using Linux open source driver and application. Do you have any experience to share?

Thanks

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