Avalon Streaming to UDP Offload example

[Altera_Forum]

I've been working through my troubles with the UDP offload example and have successfully implemented this as described in the Wiki. I am now pushing into my next portion of the project, injecting my payload via an Avalon streaming source that will replace the PRBS generator. 

 Setup:  Mixed width DCFIFO instantiated to accept 8-bit data and output 32-bit data as required by the UDP Payload inserter. PRBS Generator verilog as a base for the module  Issues:  1. I have my Source Valid tied to (SW enable and Sink Ready) -- Doing this my module will respond with a valid signal every time the UDP payload and following chain are "ready". This works OK except: I am passing invalid data as my FIFO does not respond quickly, therefore, my packets have 4 or 5 copies of the same data until a new word is processed.  2. To mitigate the issue I've tried delaying the valid signal to assert upon FIFO valid, a signal indicating new data is ready. This works for a period of time, and then the UDP payload chain "stalls". The ready bit of all items drops to '0'. This amount of time seems variable depending on the amount of delay associated with asserting the valid signal. My latest attempt gets to 1014 / 1024 bytes. previous attempts had 512, 516, ie random amounts.   My investigation into the avalon streaming interface seems that what I am doing is completely valid. If a sink ready = '1' and source valid = '0' no data is transmitted, but that only seems to hold true to a point. TSE MAC is auto negotiating to communicate at 1000Mbps; however, I attempted this at 100Mbps as well just in case my FIFO valid delay was causing some link speed issues?? Obviously not the case.  Please any help would be greatly appreciated, I must be doing something wrong but I can't figure out what and why the avalon streaming breaks down if I delay my source valid signal.  Thanks!

[Altera_Forum]

Figured it out.. interestingly enough, the UDP Payload inserter and PRBS Generator are not true avalon streaming interfaces. They make use of the format, but pin the Data Valid signals as soon as you enable the "go bit" via the Nios interface. 

 A little mucking around there to support the true flow control designed into the interface and everything seems to be moving through again.  If anyone is interested I can post my modifications.

[Altera_Forum]

Hey blazina912,  

 thanks for writing down your feedback, i also figured out that the UDP Inserter and Generator are not really compatible with all other IP-cores with the same Interface, thats why im trying wo adapt the UDP Inserter IP-core to work with the Testpattern Generator IP-Core.   can you give me any tips how modify my core the make it working ?  I really hope u are still acitve in the foroum :D Jalayan