Modern MLC flash devices require that a large number of errors be corrected (up to 32 or even 40). BCH error correction is usually suggested or assumed. However, there don't seem to be any BCH cores available, even though the BCH algorithm is clearly embedded in other IP which is available. Does anyone know why BCH cores aren't available?
We at Octera have developed a BCH core, but having done so, and comparing it to Reed-Solomon, it appears to me that Reed-Solomon may be the way to go instead of BCH. The key is to generate a Reed-Solomon core with a symbol wider than the usual 8 bits. For example, with 12-bit symbols, the message can be up to 4095 symbols long which is 4095*12 = 49140 bits. That is long enough to handle a flash page. The number of errors can be set to 32 by using 64 check symbols. Although this is overkill since it can correct 32 symbols when only 32 bits were needed, it is acceptable. In spite of this overkill, a Reed-Solomon decoder uses fewer gates than a BCH decoder. So, the second question: Does anyone know why Reed-Solomon isn't used and recommended for flash error correction? Thanks Laury Octera Corp. email@example.com