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Yannick
Novice
50 Views

Backpressure in with UART IP

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Hello everyone,

 

At the moment I am testing a system on a Cyclone V GT Development Kit with Quartus Prime Lite 20.1.

The part that is giving me problems is transfering data from a DDR3 to the TX of a UART interface. My plan was to use a MSGDMA IP with 2 Master ports to connected to the slave ports of the UART Core IP and that of the DDR3 memory interface.

All 3 components work well when tested separately. And even when connected, the datapath shows some results in a loopback configuration. The problem I however saw is that the UART is only transmitting a part of the given data.

My theory is that the UART doesn't apply backpressure (as implied in the documentation). Therefore, the MSGDMA just overruns the UART with data and every once in a while the UART actually transmits one byte.

 

My question is basically if I have overlooked a way to have a UART with backpressure?

 

I also thought about having a dual-clock FIFO but then the UART side would require a clock equal to the baud-rate. So far I didn't find a good way to implement that.

 

Best regards,

Yannick

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1 Solution
Yannick
Novice
35 Views

A short update:

I just implemented a UART IP that applies backpressure with the "ready" signal of an avalon streaming sink interface. The altera course on how to import custom IP into QSYS was very helpful for that.

The system is tested and behaves very well now. 

From my side the topic could be archived

View solution in original post

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Yannick
Novice
36 Views

A short update:

I just implemented a UART IP that applies backpressure with the "ready" signal of an avalon streaming sink interface. The altera course on how to import custom IP into QSYS was very helpful for that.

The system is tested and behaves very well now. 

From my side the topic could be archived

View solution in original post

Reply