Beats Per Symbol in Custom SOPC Components

[Altera_Forum]

Hello, 

 Is there anything special that needs to be done in custom sopc components in order for them to convert between bus widths (using varying symbols per beats?)   I am trying to go from a 32 bit to 16 bit video pipeline and have created a pixel converter based on the existing one as the Video Sync Generator appears to be 'immune' to the dynamic bus sizing.  When I try and use my new component however the display is a mess and I can tell from the appearance of the H/Vsync periods on the screen the video sync generator is either being starved of data or just not recieving the SOP/EOP signals correctly.   The existing pixel converter seems to be able to convert from 4x8bit to 1x24bit so I am not sure what I am missing. Can anyone see anything wrong with my code below?   HDL Code: module pixel_converter_565_to_666 ( input wire clk, // clock.clk input wire reset, // .reset input wire asi_in0_data, // in0.data output wire asi_in0_ready, // .ready input wire asi_in0_valid, // .valid input wire asi_in0_eop, // .endofpacket input wire asi_in0_sop, // .startofpacket input wire asi_in0_empty, // .empty output wire aso_out0_data, // out0.data input wire aso_out0_ready, // .ready output wire aso_out0_valid, // .valid output wire aso_out0_eop, // .endofpacket output wire aso_out0_sop, // .startofpacket output wire aso_out0_empty // .empty ); assign asi_in0_ready = aso_out0_ready; assign aso_out0_valid = asi_in0_valid; assign aso_out0_eop = asi_in0_eop; assign aso_out0_sop = asi_in0_sop; assign aso_out0_empty = asi_in0_empty; assign aso_out0_data = 0; assign aso_out0_data = asi_in0_data; assign aso_out0_data = asi_in0_data; assign aso_out0_data = 0; assign aso_out0_data = asi_in0_data; // TODO: Auto-generated HDL template endmodule   TCL file: # +-----------------------------------# | module pixel_converter_565_to_666# | set_module_property NAME pixel_converter_565_to_666 set_module_property VERSION 1.1 set_module_property INTERNAL false set_module_property GROUP "" set_module_property DISPLAY_NAME pixel_converter_565_to_666 set_module_property TOP_LEVEL_HDL_FILE pixel_converter_565_to_666.v set_module_property TOP_LEVEL_HDL_MODULE pixel_converter_565_to_666 set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property ANALYZE_HDL AUTO# | # +-----------------------------------# +-----------------------------------# | files# | add_file pixel_converter_565_to_666.v {SYNTHESIS SIMULATION}# | # +-----------------------------------# +-----------------------------------# | parameters# | # | # +-----------------------------------# +-----------------------------------# | display items# | # | # +-----------------------------------# +-----------------------------------# | connection point clock# | add_interface clock clock end set_interface_property clock ENABLED true add_interface_port clock clk clk Input 1 add_interface_port clock reset reset Input 1# | # +-----------------------------------# +-----------------------------------# | connection point in0# | add_interface in0 avalon_streaming end set_interface_property in0 associatedClock clock set_interface_property in0 symbolsPerBeat 2 set_interface_property in0 dataBitsPerSymbol 8 set_interface_property in0 errorDescriptor "" set_interface_property in0 maxChannel 0 set_interface_property in0 readyLatency 0 set_interface_property in0 ASSOCIATED_CLOCK clock set_interface_property in0 ENABLED true add_interface_port in0 asi_in0_data data Input 16 add_interface_port in0 asi_in0_ready ready Output 1 add_interface_port in0 asi_in0_valid valid Input 1 add_interface_port in0 asi_in0_empty empty Input 1 add_interface_port in0 asi_in0_eop endofpacket Input 1 add_interface_port in0 asi_in0_sop startofpacket Input 1# | # +-----------------------------------# +-----------------------------------# | connection point out0# | add_interface out0 avalon_streaming start set_interface_property out0 associatedClock clock set_interface_property out0 symbolsPerBeat 1 set_interface_property out0 dataBitsPerSymbol 18 set_interface_property out0 errorDescriptor "" set_interface_property out0 maxChannel 0 set_interface_property out0 readyLatency 0 set_interface_property out0 ASSOCIATED_CLOCK clock set_interface_property out0 ENABLED true add_interface_port out0 aso_out0_data data Output 18 add_interface_port out0 aso_out0_ready ready Input 1 add_interface_port out0 aso_out0_valid valid Output 1 add_interface_port out0 aso_out0_empty empty Output 1 add_interface_port out0 aso_out0_eop endofpacket Output 1 add_interface_port out0 aso_out0_sop startofpacket Output 1# | # +-----------------------------------    Thanks