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The doc shows the max freq for esrams in stratix 10 devices can be as high as 750Mhz. Since the other logics cannot work that fast, not even the async FIFOs, what is the best practice to interface to esram at such a fast clock?
Thanks.
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Hi,
I'm not sure what the best practice is. Let me consult my internal team and get back to you on that.
Regards,
Nurina
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Hi,
You need to add a reference clock for the eSRAM: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/archives/ug-s10-config-19-4.pdf#page=25
Regards,
Nurina
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Hi,
We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
Regards,
Nurina
P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!
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