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Altera_Forum
Honored Contributor I
2,529 Views

Butterworth Low Pass filter Implementation

Hi,  

 

In my application I need to implement high order Butterworth Low Pass filter to ~1Hz from 32bits, ~50ksps input signal. How can I evaluate the filter performance and estimate the resources for that sort of filter (size, memory, DSP Block, number of stages…, to select the right FPGA Cyclone V size)? I need to use some IP cores editor… (I will purchase the license, of course). The FIR II IP is only applying to Decimation filter and not for Butterworth kind of filter, right?  

 

Thanks a lot, 

Idan
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10 Replies
Altera_Forum
Honored Contributor I
153 Views

 

--- Quote Start ---  

Hi,  

 

In my application I need to implement high order Butterworth Low Pass filter to ~1Hz from 32bits, ~50ksps input signal. How can I evaluate the filter performance and estimate the resources for that sort of filter (size, memory, DSP Block, number of stages…, to select the right FPGA Cyclone V size)? I need to use some IP cores editor… (I will purchase the license, of course). The FIR II IP is only applying to Decimation filter and not for Butterworth kind of filter, right?  

 

Thanks a lot, 

Idan 

--- Quote End ---  

 

 

Butterworth IIR requires few mults and registers. I have also heard of FIR butterworth but it gets meaningless as the idea started from analogue era into digital equivalence and IIR did the job. your cutoff of 1/50k is too sharp for any FIR so I will go for iir definitely though will get nonlinear phase. 

 

You can get butterworth coeffs from matlab "[b,a] = butter(n,Wc) then study it while still in matlab using freqz(b,a) then implement it on fpga.
Altera_Forum
Honored Contributor I
153 Views

Hi, 

 

Yes can use cyclone V device family. 

For Knowing the resources you can design a project which is easier way to find resources required. 

Or  

Use FIR II IP Core Performance and Resource Utilization page 9. and find out resources required. 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_fir_compiler_ii.pdf 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
153 Views

 

--- Quote Start ---  

Hi, 

 

Yes can use cyclone V device family. 

For Knowing the resources you can design a project which is easier way to find resources required. 

Or  

Use FIR II IP Core Performance and Resource Utilization page 9. and find out resources required. 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_fir_compiler_ii.pdf 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

 

Hi, 

Thank you for your quick response! 

According to the FIR II IP I can't implement Butterworth Low Pass filter- only Decimation (and Interpolation and Decimation half-band…not Butterworth). Am I right?
Altera_Forum
Honored Contributor I
153 Views

Hi, 

 

Yes FIR II IP supports Interpolation and Decimation. 

But as suggested you can use IIR. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
153 Views

 

--- Quote Start ---  

According to the FIR II IP I can't implement Butterworth Low Pass filter- only Decimation (and Interpolation and Decimation half-band…not Butterworth). Am I right? 

--- Quote End ---  

 

No. The FIR core can implement any kind of single- and multi-rate FIR filters, including decimation and interpolation filters. Butterworth filters are originally defined by polynomials (corresponding to an IIR topology). It's however possible to implement it as an FIR approximation. Filter coefficients can be calculated e.g. by Matlab or Nuhertz Filter Solutions tool. 

 

You should be aware of a relation between fs/fc ratio and required number of FIR taps. A ratio of 50 k can be only effectively implemented as a multi-rate filter, the number of taps of a single rate is also in the fs/fc order of magnitude. In a usual IIR implementation, large fs/fc corresponds to a large extra bitwidth (log2 fs/fc) of the internal registers which is doubled for a second order biquad building block. This means, implementing a high order IIR filter with large fs/fc ratio is rather demanding. To reduce the internal bitwidth in higher order filters, it's possible to use an alternative topology similar to lattice wave digital filters.
Altera_Forum
Honored Contributor I
153 Views

Hi, 

Thank you all- it's been very helpful! 

I will read more about multi-rate filter, MATLAB function (and load the coefficients from a file), lattice wave digital filters and so on… 

Idan
Altera_Forum
Honored Contributor I
153 Views

I believe we put you on the hard bumpy track 

Anand's response on behalf of Intel is too empty for such responsibility but thanks anyway for contributing 

FvM has shrouded it with too much complexity. After all multi rate approach will require its own filter or chain of filters.  

 

Away from butterworth or no butterworth you better define your filtering requirement in terms of cutoff frequency, attenuation in dB ...etc. You want a proper filter rather specifically butterworth type.
Altera_Forum
Honored Contributor I
153 Views

 

--- Quote Start ---  

FvM has shrouded it with too much complexity. 

--- Quote End ---  

 

Might be. My first point was to clarify that a low-pass filter can be designed with the FIR II compiler, but fs/fc of 50k is only feasible as multi-rate design. 

 

I agree with kaz, that IIR is the better choice in this case. I feeled obliged to mention, that IIR implementation with high fs/fc ratio involves some problems too. A standard digital implementation of the second order building block for 1Hz@50kS/s needs about 27 extra fractional bits in the internal registers to avoid quantization errors. But that's manageable. 

 

I also agree that you should give a filter specification.
Altera_Forum
Honored Contributor I
153 Views

 

--- Quote Start ---  

Might be. My first point was to clarify that a low-pass filter can be designed with the FIR II compiler, but fs/fc of 50k is only feasible as multi-rate design. 

 

I agree with kaz, that IIR is the better choice in this case. I feeled obliged to mention, that IIR implementation with high fs/fc ratio involves some problems too. A standard digital implementation of the second order building block for 1Hz@50kS/s needs about 27 extra fractional bits in the internal registers to avoid quantization errors. But that's manageable. 

 

I also agree that you should give a filter specification. 

--- Quote End ---  

 

 

 

Hi, 

Interesting... how did you calculate the "27 extra fractional bits in the internal registers" from the 1Hz@50kS/s requirement? 

I'm now working to simulate it in the Simulink environment using DSP builder. Will I see those kind of restriction?  

Idan
Altera_Forum
Honored Contributor I
153 Views

The number of extra fractional bits can be estimated from the small numerator coefficient of the 2nd order block (about 1.6e-8). Word length effects can be simulated with Matlab fixed point package, I presume also with DSP builder.

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