FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5890 Discussions

can anyone help me about altmemphy ddr2 problem? about how to contrl initialization?

Altera_Forum
Honored Contributor II
793 Views

hi,thx first. 

i have download many pdf files,and modlesim can get waves,simulation OK,can clearly know how initialization works.but i have no idea about how to use the alememphy files to design a ddr2 chip. 

such as use what order to initialization the ddr2,or read,or write?how to control signals such as local_address,local_write_req,local_read_req etc?which file is the top level entry?ddr2.v or ddr2_example_top.v? 

■NOP (for 200 µs, programmable) 

■ PCH 

■ ELMR, register 2 

■ ELMR, register 3 

■ ELMR, register 1 

■ LMR 

■ PCH 

■ ARF 

■ ARF 

■ LMR 

■ ELMR, register 1 

■ ELMR, register 1 

how to contrl phy work to finish these work? 

thx a lot,need help
0 Kudos
0 Replies
Reply