C10 HDMI VIP

[JLee25]

Hi,

I am testing the C10 GX HDMI VIP reference design.

https://fpgacloud.intel.com/devstore/platform/18.0.1/Pro/cyclone-10-gx-hdmi-4kp60-with-video-and-image-processing-pipeline-reference-design/

And I noticed that the frame buffer setting of this project is configured to 512-bit instead of 256-bit.

I suppose 256-bit shall meet the connection requirement.

Why you use 512 instead?

BRs,

Johnson

[Deshi_Intel]

HI Johnson,

You are right. For 32 bit DQ DDR3, we only need 256 bit width to interact with the frame buffer.

The existing design of 512 bits on the frame buffer is to reserved for future expansion plan.

Thanks.

Regards,

dlim

[JLee25]

Hi dlm,

Thank you for the reply.

Regards,

Johnson

[Deshi_Intel]

You are welcome !