CYCLONE V PLL issue

[ABenj2]

I'm using Quartus 18.1 ,

The source clock, output clock, reset signal and locked signal can be viewed on test pins (see attached scope capture). 

All VCCA_FPLL pins are driven from a 2.5V source. and I check all the other voltage.

My board has 3 independent channels connected to the same host interface

After Instantiation of the PLL intel FPGA IP in my design program on a Cyclone V (5CEFA5U19I), we observe on the scope that the CLKOUT stops running after a few seconds or less (see attached pictures); the clock input is reliable but the LOCK signal is enabled after a very long time (300 msec) and indicate some problems to reach the desired clock.

It's important to notify that without using PLL all the designs run well, I can run the design with the existing clocks and create the 50 Mhz with a simple divider, the problem is that I need to add phase on the CLK and without PLL  it's not optimal.

SOME FACTS & Observations

1. When disconnecting one channel (by removing its fuse)  the CLKOUT of the defective channel did not stop after many seconds and ran well.

2. When disconnecting 2 channels (by removing its fuse)  the CLKOUT of the defective channel did not stop after many seconds and ran well.

3. Replace the 40MHz oscillator with a more stable one (15ppm instead 50ppm) and we observe that the CLKOUT runs for even more than 700 milliseconds before stopping.

4. Change the LTC3411A (Voltage Regulator of the 1.1V FPGA Core Voltage) by an external voltage regulator module we observe that the CLKOUT runs for even more than 2  seconds before stopping.

5. Adding a large decoupling capacitor (100uF)  to the output of each voltage regulator did not solve the problem.

thank you,

[Ash_R_Intel]

Hi,

There could be many reasons for PLL to loose the lock. I recommend you to go through this checklist and try to find if everything is in place.

https://cdrdv2.intel.com/v1/dl/getContent/652735?explicitVersion=true&wapkw=pll%20lock%20checklist

Regards

[ABenj2]

Hello 

I have revised my PCB and added a ground plane beneath the voltage regulator. However, I am still experiencing issues with the PLL not working on some channels. When measuring the voltage on the RREFֹTL pin, I am seeing 0V. I believe this may be indicative of a problem. What steps would you recommend I take to resolve this issue?

regards