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Cyclone V with RapidIO ip core

osi-hw
Novice
583 Views

Hi,

I want to simulate Rapidio passthrough avalont Streaming on cyclone V (Questasim) but I do not manage to have a link between the first rapidio (instance A)  and the sister rapidio (instance B).

I noticed that the port_initiliazed is always at 0. 

PS: I followed the same procedure as in this link: 

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-avalon-st-interface.html 

 

Here is the waveform that I get from this simulation on cyclone V

SIMURIO.PNG

Thanks,
BR,

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1 Solution
Kshitij_Intel
Employee
505 Views

Hi,


Please refer these Cyclone V Rapid IO example design.


https://community.intel.com/t5/FPGA-Wiki/RapidIO-Example-Design/ta-p/736028


and also please refer the debug checklist as well.


https://community.intel.com/t5/FPGA-Wiki/RapidIO-Gen1-Debug-Checklist/ta-p/736030


Thank you

Kshitij Goel


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5 Replies
Kshitij_Intel
Employee
559 Views

Hi,


Can you please generate the simulation model for the RapidIO II IP Core and run the testbench.


https://www.intel.com/content/www/us/en/docs/programmable/683444/20-3/rapidio-ii-ip-core-testbench-files.html


Also, you can refer to the reference design as well.


https://www.intel.com/content/www/us/en/docs/programmable/683197/current/downloading-and-installing-the-reference.html


Hope this will resolve your issue.


Thank you

Kshitij Goel


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osi-hw
Novice
522 Views
Hi Thank you for your reply.
The link you sent me is amreafy on my first comment.
When I run the simulation for the stratix 10 which is the device ised on the reference design. everything works fine.
But when I reproduce this design for the cyclone V it does not work because it is not the same family and not the same ip core.
so no it does not solve the issue.
Best Regards.
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Kshitij_Intel
Employee
508 Views

Hi,


Can you please share the .qar(i.e. quartus archived project).


Thank you

Kshitij Goel


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Kshitij_Intel
Employee
506 Views

Hi,


Please refer these Cyclone V Rapid IO example design.


https://community.intel.com/t5/FPGA-Wiki/RapidIO-Example-Design/ta-p/736028


and also please refer the debug checklist as well.


https://community.intel.com/t5/FPGA-Wiki/RapidIO-Gen1-Debug-Checklist/ta-p/736030


Thank you

Kshitij Goel


Kshitij_Intel
Employee
460 Views

Hi,


As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

 

Thank you

Kshitij Goel


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