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Intel MAX 10 FFT bad works

TKapi
Novice
120 Views

Hi,

I am using Quartus 22.1 (the problem was in 21.1 the same). IP configuration is attached.

The first anomaly:
sink_sop and sink_eop are every 128clk, but the source_sop and source_eop are randomly. Sometime every 127clk, sometime 128clk. Is it normal?

Input data are 0x0...0x3FF, sinus. But the output is not repeatable.
I am using BeMicro Max10 with 10M08, it is a small for bigger FFT. But in our project is 10M50, it is bigger. But for testing and pinning is better for me demoboard..

I tried sampling the input data and then inserted to Matlab and the FFT output was OK.

My first example for my project was (only first half with FFT):
https://community.intel.com/t5/FPGA-Wiki/DSP-Basic-Design-Examples/ta-p/735472

I checked the edges and they should be correct according to the datasheet and the example.

 

I am doing something wrong? Is the problem in the configuration?

 

Thank you, Tomas

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3 Replies
Kshitij_Intel
Employee
77 Views

Hi,


Can you please share your project(.qar) with below details.


1) Which Operating system you are using?

2) Which Quartus Software version you are using?

3) Which device(OPN) you are targeting?



Thank you

Kshitij Goel


TKapi
Novice
48 Views

Hi,

1) Which Operating system you are using - Windows (10 and 11)

2) Which Quartus Software version you are using - Quartus Prime Standard 22.1

3) Which device(OPN) you are targeting - BeMicro Max 10 FPGA KIT (from Arrow), with 10M08DAF484C8GES


My qar is attached.

 

Thank you, Tomas

TKapi
Novice
13 Views

Hi,

I tried differet FFT settings and different FPGA size.

FPGA: 10M25SAE144I7G

new.png

Now, I have another, but similar, problem. The signal source_sop has double size (it takes two clocks of clk). Is it normal?

1.png

ZOOM:

2.png

3.png

What could be the cause? Has the clk signal any restrictions? My clk frequency is 390 Hz.

 

Thank you, Tomas

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