Hello ,
Can I use Arria10 PLL on differential clock?
yes , Setup the IO pins std with the correct differential IO standards and use the positive pin into the PLL input and fitter should be able to infer the negative pole of the differential input by itself (since it is set as differential std).
Can I feed a differential clock to the PLL and configure the PLL to generate another differential clock?
Actually i am not sure i follow the question here ., but let me explain one thing here , In the FPGA design you would only see single line (RTL level) even for differential signal. The differential signaling is generally at the IO portion (Buffer). Inside the FPGA, the signal is single ended. You would only need to assign your input/output pin with differential IO standard and placed them to differential pins.
For the pIn level yes , you can use the PLL dedicated output as the differential , Kindly go through the pin out documentation based on your device plan to use.
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
What type of PLL should I use for differential clock?
Hope you meant by IOPLL, FPLL or DPLL etc .It depends on what you plan to do with the PLL output.For example if you would like to use the PLL for the core logic , you can use IOPLL. I meant to say select the pll type based on what you wanted to do with it.
user guide PLL link is given for the reference
https://www.intel.com/content/www/us/en/programmable/documentation/sam1403483633377.html#sam1403481655451
Thank you ,
Regards,
Sree
