Cannot Read data from MAX10 UFM

[Stephanie]

I am unable to read data from a MAX 10 UFM IP.  I'm using the On-Chip Flash Intel FPGA IP, trying read only memory for sector 1, and initializing the data with 125 values with both the .mif file for synthesis and a .dat file for simulation. In simulation when I try to read from the UFM, all addresses give me XXXXXXX. At startup the values from the readdata value is 11111111, once I intiate a read it goes to 00000000 and once readdata_valid asserts the data updates to XXXXXXXX. I would appreciate any help on this! 

Thank you! 

[YuanLi_S_Intel]

Have you selected burst count after you assert the read signal?

You may follow the user guide available at link below for the steps to perform read operation:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_ufm.pdf (Page 16)

[Stephanie]

I believe I am following the User Guide. avmm_burstcount is set at the same time avmm_read is asserted, I'll attach a waveform. 

[Stephanie]

Is there any more feedback for this issue? 

[Stephanie]

I also get the following warning messages throughout the simulation: 

# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'the_master_to_user_fifo'. Expected 13, found 8.
# Time: 0 ps Iteration: 0 Instance: /testbench/UUT/master/the_master_to_user_fifo File: C:/MAX10_work/burst_read_master.v Line: 237
# ** Warning: (vsim-3722) C:/MAX10_work/burst_read_master.v(237): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) C:/MAX10_work/burst_read_master.v(237): [TFMPC] - Missing connection for port 'eccstatus'.
# ** Warning: (vsim-3722) C:/MAX10_work/burst_read_master.v(237): [TFMPC] - Missing connection for port 'full'.
# ** Warning: (vsim-3722) C:/MAX10_work/burst_read_master.v(237): [TFMPC] - Missing connection for port 'almost_full'.
# ** Warning: (vsim-3722) C:/MAX10_work/burst_read_master.v(237): [TFMPC] - Missing connection for port 'almost_empty'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'flash'. Expected 15, found 10.
# Time: 0 ps Iteration: 0 Instance: /testbench/UUT/flash File: C:/MAX10_work/MAX10_work.v Line: 148
# ** Warning: (vsim-3015) [PCDPC] - Port size (17) does not match connection size (32) for port 'avmm_data_addr'. The port definition is at: C:/MAX10_work/max10_flash/simulation/max10_flash.v(13).
# Time: 0 ps Iteration: 0 Instance: /testbench/UUT/flash File: C:/MAX10_work/MAX10_work.v Line: 148
# ** Warning: (vsim-3722) C:/MAX10_work/MAX10_work.v(148): [TFMPC] - Missing connection for port 'avmm_csr_addr'.
# ** Warning: (vsim-3722) C:/MAX10_work/MAX10_work.v(148): [TFMPC] - Missing connection for port 'avmm_csr_read'.
# ** Warning: (vsim-3722) C:/MAX10_work/MAX10_work.v(148): [TFMPC] - Missing connection for port 'avmm_csr_writedata'.
# ** Warning: (vsim-3722) C:/MAX10_work/MAX10_work.v(148): [TFMPC] - Missing connection for port 'avmm_csr_readdata'.
# ** Warning: (vsim-3722) C:/MAX10_work/MAX10_work.v(148): [TFMPC] - Missing connection for port 'avmm_data_writedata'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'ufm_data_shiftreg'. Expected 11, found 6.
# Time: 0 ps Iteration: 0 Instance: /testbench/UUT/flash/onchip_flash_0/avmm_data_controller/genblk6/ufm_data_shiftreg File: C:/MAX10_work/max10_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1175
# ** Warning: (vsim-3722) C:/MAX10_work/max10_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Missing connection for port 'shiftin'.
# ** Warning: (vsim-3722) C:/MAX10_work/max10_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Missing connection for port 'aset'.
# ** Warning: (vsim-3722) C:/MAX10_work/max10_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) C:/MAX10_work/max10_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) C:/MAX10_work/max10_flash/simulation/submodules/altera_onchip_flash_avmm_data_controller.v(1175): [TFMPC] - Missing connection for port 'q'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'altera_onchip_flash_block'. Expected 18, found 17.
# Time: 0 ps Iteration: 0 Instance: /testbench/UUT/flash/onchip_flash_0/altera_onchip_flash_block File: C:/MAX10_work/max10_flash/simulation/submodules/altera_onchip_flash.v Line: 302
# ** Warning: (vsim-3722) C:/MAX10_work/max10_flash/simulation/submodules/altera_onchip_flash.v(302): [TFMPC] - Missing connection for port 'bgpbusy'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for '<protected>'. Expected <protected>, found <protected>.
# Time: 0 ps Iteration: 0 Protected: /testbench/UUT/flash/onchip_flash_0/altera_onchip_flash_block/inst/<protected>/<protected>/<protected>/<protected>/<protected> File: $MODEL_TECH/../altera/verilog/src/mentor/fiftyfivenm_atoms_ncrypt.v Line: 38
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.

testbench.UUT.flash.onchip_flash_0.altera_onchip_flash_block.inst.<protected>.<protected>.<protected>.<protected>.<protected>.<protected>: 1.25ns: WARNING: DIN shows unknown state!

testbench.UUT.flash.onchip_flash_0.altera_onchip_flash_block.inst.<protected>.<protected>.<protected>.<protected>.<protected>.<protected>: 1.25ns: WARNING: DIN shows unknown state!

[YuanLi_S_Intel]

Hi,

From the warning message, seems like the connection is not completed. It would be better if you could connect the IP and your testbench properly as per the user guide.

Thank You.