Chaining DMA PCIe Reference Design freezes when Cpl with a "non-successful" Status

[Altera_Forum]

The Chaining DMA PCIe Reference Design does not handle Completions with a "non-successful status".  

 For example, I had accidentally set the Host Address to read from the wrong place in my MRd Request. This caused the RC to send a Cpl with Status set to Unsupported Request ("001"). After this the DMA engine freezes up because it never sets rx_ack high.  In order to get around this, update altpcierd_read_dma_requester_128.vhd as below:    PROCESS (clk_in)  BEGIN  IF (clk_in'EVENT AND clk_in = '1') THEN  IF (rx_req_p0 = '0') THEN  rx_dmard_cpld <= '0';             rx_dmard_cpl_stat_not_success <= '0';  ELSE             IF ((rx_dfr = '1') AND (rx_fmt = "10") AND (rx_type = "01010")) THEN  rx_dmard_cpld <= '1';  ELSIF ( (rx_fmt = "00") AND (rx_type = "01010") AND (rx_cpl_stat /= "000") ) THEN          --Read Completion with Completion Status other than Successful Completion.              rx_dmard_cpl_stat_not_success <= '1';  END IF;[/INDENT]  END IF;[/INDENT]  END IF;[/INDENT]  END PROCESS;[/INDENT]   -- Set/Clear rx_ack  rx_ack <= '1' WHEN ((nstate_rx = CPLD_ACK_3 ) OR (rx_dmard_cpl_stat_not_success = '1')) ELSE  '0';  Another minor bug is that the case when you have a 64bit machine, the address supplied by the host is 32bit (< 4GB), and you are not in the ep lastupd cycle, the dma engine uses the wrong TLP format.   In order to get around this, update altpcierd_read_dma_requester_128.vhd as below:   tx_desc_fmt_64 <= "10" WHEN ((ep_lastupd_cycle = '1') AND (dt_3dw_rcadd = '1')) ELSE                      "00" WHEN ((ep_lastupd_cycle = '0') AND (dt_3dw_rcadd = '1')) ELSE --Spec: "For Addresses below 4 GB, Requesters must use the 32-bit format."  "11" WHEN ((ep_lastupd_cycle = '1') AND (dt_3dw_rcadd = '0')) ELSE  "01";[/INDENT][/INDENT]  Hope someone at Altera is looking at this and fixes this in the next release.:)

[Altera_Forum]

Just saw that in the Verilog version of the CDMA reference design, the 2nd bug i mentioned (tx_desc_fmt_64) has been resolved. The VHDL version is converted from the Verilog version (using XHDL I think) and I must not have the most updated version.  

 Is there a up to date VHDL version of the CDMA reference design?

[Altera_Forum]

Haven’t looked at the DMA design example for some months now, but assuming that nothing has changed in this regard, it does not support any completion timeout mechanism. So, it’s nice that the RC returns 001 in your case, but eventually it may not respond at all, and the DMA will again hang. 

 – Matthias